Verific Unveils Perl Interface for Its SystemVerilog, VHDL Front-End Solutions
Verific Design Automation, long known for its SystemVerilog and VHDL front-end solutions used by leading EDA, FPGA and semiconductor companies worldwide, today unveiled a Perl interface to its...
View ArticlevSync Circuits Licenses Verific Design Automation’s Parser Platform
Verific Design Automation, supplier of industry-standard, IEEE-compliant hardware description language (HDL) front-end solutions, today announced vSync Circuits Ltd. in Israel has licensed its parser...
View ArticleVerific Design Automation Adds UPF 2.0 Support to Growing Parser Platform
Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, today announced immediate availability of a parser for the IEEE 1801-2009 Standard...
View ArticleVerific Design Automation Selected to Support Blue Pearl Software Suite
Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL front-end solutions, has been selected by Blue Pearl Software to support its Blue Pearl Software Suite....
View ArticleVerific Exhibits at 49th Design Automation Conference and Hosts DAC Tuesday...
WHO: Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators WHAT: Will exhibit at the 49th Design Automation Conference in booth #1807...
View ArticleVerific Design Automation’s Industry-Standard SystemVerilog, VHDL Parsers...
Verific Design Automation today announced it licensed its industry-standard, IEEE-compliant SystemVerilog and VHDL platform to Aldec, Inc., a global leader in electronic design verification, to be...
View ArticleInvionics Unveils VRDM Development Platform for Rapid Deployment of Verific...
Easy-to-Use, Scriptable Interface Reduces Costs, Accelerates Development of Tools, Flows
View ArticleVerific Invites DAC Attendees to Visit Booth for Giraffe Giveaway, Learn...
Twenty-Four Partners Exhibiting at DAC
View ArticleVtool Relies on Verific Design Automation’s Parser Platform to Drive...
Verific’s Parser Platform Ensures Integration With SystemVerilog and UVM
View ArticleVerific Design Automation’s Parser Platform Integrated With Tortuga Logic’s...
Thoroughly Tested Parsers Let Tortuga Logic Focus on Software to Identify Security Vulnerabilities in Hardware Designs
View ArticleVerific Acquires INVIO Platform from Invionics Software
Rapid Application Development Platform will be added to Verific’s Parser Platform
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